The present invention relates to a nonvolatile semiconductor device and a method for testing the same, and more specifically, to a technology for controlling a write operation of a nonvolatile memory device configured to sense data based on resistance change.
Generally, memory devices may be classified as volatile memory devices or nonvolatile memory devices. A nonvolatile memory is device includes a nonvolatile memory cell capable of preserving stored data even when a power source is off. A nonvolatile memory device may be implemented, for example, as a flash random access memory (RAM) device, a phase change RAM (PCRAM) device, or the like.
PCRAM devices include memory cells that are implemented using a phase change material, for example, germanium antimony tellurium (GST), and are configured to store data in the memory cells by applying heat to the GST so that the GST changes into a crystalline phase or an amorphous phase.
A nonvolatile memory device, such as a magnetic memory device, a phase change memory (PCM) device, or the like, has a data processing speed similar to that of a volatile RAM device. A nonvolatile memory device also preserves data even when a power source is off.
FIGS. 1a and 1b illustrates a conventional phase change resistance device 4.
Referring to FIGS. 1a and 1b, a conventional phase change resistance device 4 includes an upper electrode 1, a lower electrode 3, and a phase change material 2 interposed between the upper electrode 1 and the lower electrode 3. When a voltage is applied to the upper electrode 1 and the lower electrode 3, a current flows into the phase change material 2, thus inducing a high temperature in the phase change material 2. As a result, the electrical conductive state of the phase change material 2 changes depending on resistance variation due to the high temperature.
FIGS. 2a and 2b illustrates a phase change principle of the conventional phase change resistance device 4.
Referring to FIG. 2a, if a low current smaller than a critical value flows into the phase change resistance device 4, the phase change material 2 is crystallized. When the phase change material 2 changes into a crystalline phase, it becomes a low resistance material. As a result, a current can flow between the upper electrode 1 and the lower electrode 3.
On the other hand, referring to FIG. 2b, if a high current greater than the critical value flows into the phase change resistance device 4, the phase change material 2 has a temperature higher than a quenching point. When the phase change material 2 changes into an amorphous phase, i.e., a non-crystalline phase, it becomes a high resistance material. As a result, a current cannot easily flow between the upper electrode 1 and the lower electrode 3.
The phase change resistance device 4 can store data corresponding to two resistance phases. That is, in one case, if a low resistance phase in the phase change resistance device corresponds to a data “1,” and the high resistance phase corresponds to a data “0,” then the phase change resistance device 4 may store two logic states of data.
This data can be stored in the phase change resistance device 4 as nonvolatile data because the status of the phase change material 2 does not change even when a power source is off.
FIG. 3 illustrates a write operation of a conventional phase change resistance cell.
Referring to FIG. 3, heat is generated if a current flows between the upper electrode 1 and the lower electrode 3 of the phase change resistance device 4 for a given time.
If a low current, smaller than the critical value, flows for the given time, the phase change material 2 changes into a crystalline phase. As a result, the phase change resistance device 4 becomes a low resistance element having a set phase.
On the other hand, if a high current, greater than the critical value, flows for a given time, the phase change material 2 changes into an amorphous phase. As a result, the phase change resistance device 4 becomes a high resistance element having a reset phase.
Accordingly, a low voltage is applied to the phase change resistance device 4 for a long period of time in order to write the set phase in the write operation.
On the other hand, a high voltage is applied to the phase change resistance device 4 for a short period of time in order to write the reset phase in the write operation.
To change the phase change resistance cell into the set phase, it is important to control a quenching slope of a set write current, which is required for crystalizing the phase change resistance cell, by gradually reducing an amount of the set write current. This way of gradually reducing the set write current is called “quenching.”
However, for example, if a reference current, which is used to generate the set write current and is received from the outside or generated inside the chip, changes by some factors or if a clock having a wrong value is generated by mismatched circuits, the set write current may be generated to have an undesired quenching slope.
Moreover, without accurately checking the quenching slope, it is impossible to precisely control the phase change resistance cell in program and verify (PNV) operations and a multi-level cell MLC where multi-leveled resistance distribution of a phase change material, e.g., germanium antimony tellurium (GST), is formed.